Codasip, the leader in RISC-V Custom Compute, has today announced its collaboration with Siemens EDA to offer its customers the Tessent Enhanced Trace Encoder solution from the Tessent Embedded Analytics product line. Through the joint solution, developers will be able to efficiently trace and debug issues between silicon and software and accurately understand the real-time behaviours of complex customised designs based on Codasip’s RISC-V processors.
Achieving Custom Compute is made possible through Codasip’s fully customisable and adaptable RISC-V processors, combined with its Studio toolchain and its accompanying suite of supported tools including the compiler and debugger, now including the trace solution.
Mike Eftimakis, VP Strategy and Ecosystem at Codasip, commented, “Codasip has high standards of quality when it comes to our processor IP. To ensure this results in outstanding systems, we wanted a trace solution that went much further than the RISC-V standard. The Tessent Enhanced Trace Encoder is optimized for exactly the types of complex and custom systems our customers are developing.”
Including trace in an SoC is designed to significantly speed up software debug tasks and reduce the bring-up time and cost of software development. The Tessent Enhanced Trace Encoder builds on the RISC-V standard produced by the Debug and Trace Working Group, and goes beyond the RISC-V standard by offering a far more efficient tool with significant productivity gains for even the most complex heterogeneous and custom designs.
Ankur Gupta, VP and GM of Siemens EDA’s Tessent division, said “Tessent Embedded Analytics enables system-wide real-time debug and post-deployment analytics, helping SoC providers focus on the key task of producing high-quality, innovative products, and getting them to market quickly. Codasip has an outstanding reputation for assisting customers with just these kinds of requirements, and we’re delighted to be working together.”
Codasip will offer the Tessent Enhanced Trace Encoder solution directly to customers to streamline contractual complexity.
Today Codasip and Siemens EDA have announced their collaboration to offer customers the Tessent Enhanced Trace Encoder solution from the Tessent Embedded Analytics product line. Through the joint solution, developers will be able to efficiently debug software and hardware issues and accurately understand the behaviour of complex customised designs based on Codasip’s RISC-V processors.
Mike Eftimakis, VP Strategy and Ecosystem at Codasip, said: “Codasip has high standards of quality when it comes to our processor IP. To ensure this results in outstanding systems, we wanted a trace solution that went much further than the RISC-V standard. The Tessent Enhanced Trace Encoder is optimized for exactly the types of complex and custom systems our customers are developing.”
Ankur Gupta, VP and GM of Siemens EDA’s Tessent division, added: “Tessent Embedded Analytics enables system-wide real-time debug and post-deployment analytics, helping SoC providers focus on the key task of producing high-quality, innovative products, and getting them to market quickly. Codasip has an outstanding reputation for assisting customers with just these kinds of requirements, and we’re delighted to be working together.”
The Tessent Enhanced Trace Encoder builds on the RISC-V standard produced by the Debug and Trace Working Group, offering a far more efficient tool with significant productivity gains for even the most complex heterogeneous and custom designs. It is designed to speed up software debug tasks, reducing the bring-up time and cost of software development.
Codasip will offer the Tessent Enhanced Trace Encoder solution directly to customers to streamline contractual complexity.
The post Siemens and Codasip Team Up to Offer Trace Solution for Custom Processors first appeared on BusinessMole.
